Electro-optic displays, and components for use therein

ABSTRACT

An electro-optic display comprises a substrate ( 100 ), non-linear devices ( 102 ) disposed substantially in one plane on the substrate ( 100 ), pixel electrodes ( 106 ) connected to the non-linear devices ( 102 ), an electro-optic medium ( 110 ) and a common electrode ( 112 ) on the opposed side of the electro-optic medium ( 110 ) from the pixel electrodes ( 106 ). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices ( 102 ).

REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 11/560,459,filed Nov. 16, 2006 (Publication No. 2007/0069247), which itself is adivisional of application Ser. No. 10/904,160, filed Oct. 7, 2004(Publication No. 2005/0078099, now U.S. Pat. No. 7,190,008, issued Mar.13, 2007), which itself is a continuation-in-part of application Ser.No. 10/249,618, filed Apr. 24, 2003 (Publication No. 2003/0222315, nowU.S. Pat. No. 7,116,318), which claims benefit of Application Ser. Nos.60/375,571 and 60/375,508, both filed May 12, 2002.

The aforementioned application Ser. No. 10/904,160 also claims benefitof Application Ser. No. 60/481,565, filed Oct. 27, 2003 and ApplicationSer. No. 60/481,591, filed Nov. 3, 2003.

This application is also related to (a) copending application Ser. No.10/249,624 filed Apr. 24, 2003 (Publication No. 2004/0014265, now U.S.Pat. No. 7,223,672), which claims benefit of Application Ser. No.60/375,248, filed Apr. 24, 2002, and Application Ser. No. 60/376,603,filed Apr. 30, 2002; (b) application Ser. No. 09/565,413, filed May 5,2000 (now U.S. Pat. No. 7,030,412); (c) application Ser. No. 09/904,109,filed Jul. 12, 2001 (now U.S. Pat. No. 6,683,333); (d) application Ser.No. 10/065,795, filed Nov. 20, 2002 (Publication No. 2003/0137521, nowU.S. Pat. No. 7,012,600); (e) copending application Ser. No. 10/707,184,filed Nov. 25, 2003 (Publication No. 2004/0180476); and (f) copendingapplication Ser. No. 10/711,829, filed Oct. 7, 2004 (Publication No.2005/0168799, now U.S. Pat. No. 7,230,750).

The entire contents of the aforementioned applications are hereinincorporated by reference. The entire contents of all United Statespatents and copending and published applications mentioned below arealso herein incorporated by reference.

BACKGROUND OF INVENTION

The present invention relates to electro-optic displays and tocomponents, especially backplanes, for use in such displays. The presentinvention is especially, though not exclusively, intended for use insuch displays based on stainless steel or similar metal foil substrates.

In the displays of the present invention, the electro-optic medium willtypically be a solid (such displays may hereinafter for convenience bereferred to as “solid electro-optic displays”), in the sense that theelectro-optic medium has solid external surfaces, although the mediummay, and often does, have internal liquid- or gas-filled spaces, and tomethods for assembling displays using such an electro-optic medium.Thus, the term “solid electro-optic displays” includes encapsulatedelectrophoretic displays, encapsulated liquid crystal displays, andother types of displays discussed below. Certain aspects of the presentinvention are primarily, although not exclusively, intended for use withencapsulated electrophoretic displays.

The term “electro-optic”, as applied to a material or a display, is usedherein in its conventional meaning in the imaging art to refer to amaterial having first and second display states differing in at leastone optical property, the material being changed from its first to itssecond display state by application of an electric field to thematerial. Although the optical property is typically color perceptibleto the human eye, it may be another optical property, such as opticaltransmission, reflectance, luminescence or, in the case of displaysintended for machine reading, pseudo-color in the sense of a change inreflectance of electromagnetic wavelengths outside the visible range.

The term “gray state” is used herein in its conventional meaning in theimaging art to refer to a state intermediate two extreme optical statesof a pixel, and does not necessarily imply a black-white transitionbetween these two extreme states. For example, several of the patentsand published applications referred to below describe electrophoreticdisplays in which the extreme states are white and deep blue, so that anintermediate “gray state” would actually be pale blue. Indeed, asalready mentioned the transition between the two extreme states may notbe a color change at all.

The terms “bistable” and “bistability” are used herein in theirconventional meaning in the art to refer to displays comprising displayelements having first and second display states differing in at leastone optical property, and such that after any given element has beendriven, by means of an addressing pulse of finite duration, to assumeeither its first or second display state, after the addressing pulse hasterminated, that state will persist for at least several times, forexample at least four times, the minimum duration of the addressingpulse required to change the state of the display element. It is shownin published U.S. Patent Application No. 2002/0180687 that someparticle-based electrophoretic displays capable of gray scale are stablenot only in their extreme black and white states but also in theirintermediate gray states, and the same is true of some other types ofelectro-optic displays. This type of display is properly called“multi-stable” rather than bistable, although for convenience the term“bistable” may be used herein to cover both bistable and multi-stabledisplays.

Several types of electro-optic displays are known. One type ofelectro-optic display is a rotating bichromal member type as described,for example, in U.S. Pat. Nos. 5,808,783; 5,777,782; 5,760,761;6,054,071; 6,055,091; 6,097,531; 6,128,124; 6,137,467; and 6,147,791(although this type of display is often referred to as a “rotatingbichromal ball” display, the term “rotating bichromal member” ispreferred as more accurate since in some of the patents mentioned abovethe rotating members are not spherical). Such a display uses a largenumber of small bodies (typically spherical or cylindrical) which havetwo or more sections with differing optical characteristics, and aninternal dipole. These bodies are suspended within liquid-filledvacuoles within a matrix, the vacuoles being filled with liquid so thatthe bodies are free to rotate. The appearance of the display is changedto applying an electric field thereto, thus rotating the bodies tovarious positions and varying which of the sections of the bodies isseen through a viewing surface. This type of electro-optic medium istypically bistable.

Another type of electro-optic display uses an electrochromic medium, forexample an electrochromic medium in the form of a nanochromic filmcomprising an electrode formed at least in part from a semi-conductingmetal oxide and a plurality of dye molecules capable of reversible colorchange attached to the electrode; see, for example O'Regan, B., et al.,Nature 1991, 353, 737; and Wood, D., Information Display, 18(3), 24(March 2002). See also Bach, U., et al., Adv. Mater., 2002, 14(11), 845.Nanochromic films of this type are also described, for example, in U.S.Pat. No. 6,301,038, International Application Publication No. WO01/27690, and in U.S. Patent Application 2003/0214695. This type ofmedium is also typically bistable.

Another type of electro-optic display, which has been the subject ofintense research and development for a number of years, is theparticle-based electrophoretic display, in which a plurality of chargedparticles move through a suspending fluid under the influence of anelectric field. Electrophoretic displays can have attributes of goodbrightness and contrast, wide viewing angles, state bistability, and lowpower consumption when compared with liquid crystal displays.Nevertheless, problems with the long-term image quality of thesedisplays have prevented their widespread usage. For example, particlesthat make up electrophoretic displays tend to settle, resulting ininadequate service-life for these displays.

Numerous patents and applications assigned to or in the names of theMassachusetts Institute of Technology (MIT) and E Ink Corporation haverecently been published describing encapsulated electrophoretic media.Such encapsulated media comprise numerous small capsules, each of whichitself comprises an internal phase containing electrophoretically-mobileparticles suspended in a liquid suspending medium, and a capsule wallsurrounding the internal phase. Typically, the capsules are themselvesheld within a polymeric binder to form a coherent layer positionedbetween two electrodes. Encapsulated media of this type are described,for example, in U.S. Pat. Nos. 5,930,026; 5,961,804; 6,017,584;6,067,185; 6,118,426; 6,120,588; 6,120,839; 6,124,851; 6,130,773;6,130,774; 6,172,798; 6,177,921; 6,232,950; 6,249,271; 6,252,564;6,262,706; 6,262,833; 6,300,932; 6,312,304; 6,312,971; 6,323,989;6,327,072; 6,376,828; 6,377,387; 6,392,785; 6,392,786; 6,413,790;6,422,687; 6,445,374; 6,445,489; 6,459,418; 6,473,072; 6,480,182;6,498,114; 6,504,524; 6,506,438; 6,512,354; 6,515,649; 6,518,949;6,521,489; 6,531,997; 6,535,197; 6,538,801; 6,545,291; 6,580,545;6,639,578; 6,652,075; 6,657,772; 6,664,944; 6,680,725; 6,683,333;6,704,133; 6,710,540; 6,721,083; 6,727,881; 6,738,050; 6,750,473; and6,753,999; and U.S. Patent Applications Publication Nos. 2002/0019081;2002/0021270; 2002/0060321; 2002/0063661; 2002/0090980; 2002/0113770;2002/0130832; 2002/0131147; 2002/0171910; 2002/0180687; 2002/0180688;2002/0185378; 2003/0011560; 2003/0020844; 2003/0025855; 2003/0038755;2003/0053189; 2003/0102858; 2003/0132908; 2003/0137521; 2003/0137717;2003/0151702; 2003/0214695; 2003/0214697; 2003/0222315; 2004/0008398;2004/0012839; 2004/0014265; 2004/0027327; 2004/0075634; 2004/0094422;2004/0105036; 2004/0112750; and 2004/0119681; and InternationalApplications Publication Nos. WO 99/67678; WO 00/05704; WO 00/38000; WO00/38001; WO00/36560; WO 00/67110; WO 00/67327; WO 01/07961; WO01/08241; WO 03/107,315; WO 2004/023195; and WO 2004/049045.

Many of the aforementioned patents and applications recognize that thewalls surrounding the discrete microcapsules in an encapsulatedelectrophoretic medium could be replaced by a continuous phase, thusproducing a so-called polymer-dispersed electrophoretic display, inwhich the electrophoretic medium comprises a plurality of discretedroplets of an electrophoretic fluid and a continuous phase of apolymeric material, and that the discrete droplets of electrophoreticfluid within such a polymer-dispersed electrophoretic display may beregarded as capsules or microcapsules even though no discrete capsulemembrane is associated with each individual droplet; see for example,the aforementioned 2002/0131147. Accordingly, for purposes of thepresent application, such polymer-dispersed electrophoretic media areregarded as sub-species of encapsulated electrophoretic media.

A related type of electrophoretic display is a so-called “microcellelectrophoretic display”. In a microcell electrophoretic display, thecharged particles and the suspending fluid are not encapsulated withinmicrocapsules but instead are retained within a plurality of cavitiesformed within a carrier medium, typically a polymeric film. See, forexample, International Application Publication No. WO 02/01281, andpublished US Application No. 2002/0075556, both assigned to SipixImaging, Inc.

Although electrophoretic media are often opaque (since, for example, inmany electrophoretic media, the particles substantially blocktransmission of visible light through the display) and operate in areflective mode, many electrophoretic displays can be made to operate ina so-called “shutter mode” in which one display state is substantiallyopaque and one is light-transmissive. See, for example, theaforementioned U.S. Pat. Nos. 6,130,774 and 6,172,798, and U.S. Pat.Nos. 5,872,552; 6,144,361; 6,271,823; 6,225,971; and 6,184,856.Dielectrophoretic displays, which are similar to electrophoreticdisplays but rely upon variations in electric field strength, canoperate in a similar mode; see U.S. Pat. No. 4,418,346. Other types ofelectro-optic displays may also be capable of operating in shutter mode.

An encapsulated or microcell electrophoretic display typically does notsuffer from the clustering and settling failure mode of traditionalelectrophoretic devices and provides further advantages, such as theability to print or coat the display on a wide variety of flexible andrigid substrates. (Use of the word “printing” is intended to include allforms of printing and coating, including, but without limitation:pre-metered coatings such as patch die coating, slot or extrusioncoating, slide or cascade coating, curtain coating; roll coating such asknife over roll coating, forward and reverse roll coating; gravurecoating; dip coating; spray coating; meniscus coating; spin coating;brush coating; air knife coating; silk screen printing processes;electrostatic printing processes; thermal printing processes; ink jetprinting processes; and other similar techniques.) Thus, the resultingdisplay can be flexible. Further, because the display medium can beprinted (using a variety of methods), the display itself can be madeinexpensively.

Whether a display is reflective or transmissive, and whether or not theelectro-optic medium used is bistable, to obtain a high-resolutiondisplay, individual pixels of a display must be addressable withoutinterference from adjacent pixels. One way to achieve this objective isto provide an array of non-linear elements, such as transistors ordiodes, with at least one non-linear element is associated with eachpixel, to produce an “active matrix” display. An addressing or pixelelectrode, which addresses one pixel, is connected to an appropriatevoltage source through the associated non-linear element. Typically,when the non-linear element is a transistor, the pixel electrode isconnected to the drain of the transistor, and this arrangement will beassumed in the following description, although it is essentiallyarbitrary and the pixel electrode could be connected to the source ofthe transistor. Conventionally, in high resolution arrays, the pixelsare arranged in a two-dimensional array of rows and columns, such thatany specific pixel is uniquely defined by the intersection of onespecified row and one specified column. The sources of all thetransistors in each column are connected to a single column electrode,while the gates of all the transistors in each row are connected to asingle row electrode; again the assignment of sources to rows and gatesto columns is conventional but essentially arbitrary, and could bereversed if desired. The row electrodes are connected to a row driver,which essentially ensures that at any given moment only one row isselected, i.e., that there is applied to the selected row electrode avoltage such as to ensure that all the transistors in the selected roware conductive, while there is applied to all other rows a voltage suchas to ensure that all the transistors in these non-selected rows remainnon-conductive. The column electrodes are connected to column drivers,which place upon the various column electrodes voltages selected todrive the pixels in the selected row to their desired optical states.(The aforementioned voltages are relative to a common front electrodewhich is conventionally provided on the opposed side of theelectro-optic medium from the non-linear array and extends across thewhole display.) After a pre-selected interval known as the “line addresstime” the selected row is deselected, the next row is selected, and thevoltages on the column drivers are changed to that the next line of thedisplay is written. This process is repeated so that the entire displayis written in a row-by-row manner. Thus, in a display with N rows, anygiven pixel can only be addressed for a fraction 1/N of the time.

Processes for manufacturing active matrix displays are well established.Thin-film transistors, for example, can be fabricated using variousdeposition and photolithography techniques. A transistor includes a gateelectrode, an insulating dielectric layer, a semiconductor layer andsource and drain electrodes. Application of a voltage to the gateelectrode provides an electric field across the dielectric layer, whichdramatically increases the source-to-drain conductivity of thesemiconductor layer. This change permits electrical conduction betweenthe source and the drain electrodes. Typically, the gate electrode, thesource electrode, and the drain electrode are patterned. In general, thesemiconductor layer is also patterned in order to minimize strayconduction (i.e., cross-talk) between neighboring circuit elements.

Liquid crystal displays commonly employ amorphous silicon (“a-Si”)thin-film transistors (“TFT's”) as switching devices for display pixels.Such TFT's typically have a bottom-gate configuration. Within one pixel,a thin-film capacitor typically holds a charge transferred by theswitching TFT. Electrophoretic displays can use similar TFT's withcapacitors, although the function of the capacitors differs somewhatfrom those in liquid crystal displays; see copending application Ser.No. 09/565,413, filed May 5, 2000 (now U.S. Pat. No. 7,030,412), U.S.Patent Publication No 2002/0106847 and the aforementioned 2002/0060321.Thin-film transistors can be fabricated to provide high performance.Fabrication processes, however, can result in significant cost.

In TFT addressing arrays, pixel electrodes are charged via the TFT'sduring a line address time. During the line address time, a TFT isswitched to a conducting state by changing an applied gate voltage. Forexample, for an n-type TFT, a gate voltage is switched to a “high” stateto switch the TFT into a conducting state.

Many electro-optic materials require application of a drive voltage fora significant switching time (typically of the order of 10⁻² to 10⁻¹seconds) to effect a transition between their two extreme opticalstates. For high resolution displays containing at least (say) 100 rowsand columns, if a reasonable scan rate is to be maintained, the periodfor which an individual pixel is addressed during a single scan is muchless than the switching time of the electro-optic medium, andaccordingly much of the switching of a pixel is effected by the voltagewhich remains on the pixel electrode between successive times ofaddressing the pixel (i.e., while other columns of the display are beingaddressed). This remaining voltage gradually decays due to currentpassing through the electro-optic material of the pixel and any currentleakage through the non-linear element. The rate at which this decayoccurs can be reduced (and the average voltage applied to the pixelduring one complete scan of the display thus increased—this is commonlyreferred to as “increasing the voltage holding capacity” of the pixel)by connecting the pixel electrode to a capacitor.

At least some of the aforementioned electro-optic media can be madesufficiently flexible to permit their use in flexible displays basedupon flexible substrates such as metal or polymeric films. Some recentpublications of previous related work applied to electrophoreticdisplays on steel foil substrates and related technologies include:

-   Y Chen, P. Kazlas, K. Denis and P. Drzaic, in SID Intl. Symp. Digest    Tech. Papers, San Jose 2001 (Society of Information Display, San    Jose) p. 157;-   P. Kazlas, A. Ritenour, J. Au, Y Chen, J. Goodman, R. Paolini and H.    Gates, in 22nd IntL Display Research Conference Nice 2002 (Society    of Information Display, San Jose);-   Au, Y. Chen, A. Ritenour, P. Kazlas and H. Gates, 9th Intl. Display    Workshops Hiroshima 2002 (Society of Information Display, San Jose);-   Suo et al., Mechanics of rollable and foldable film-on-foil    electronics, App. Phys. Lett., 74, 1177 (22 Feb. 1999).

However, manufacturing flexible microelectronic backplanes for suchdisplays presents many challenges. A key problem in the manufacture andoperation of such thin film transistors on flexible substrates is thinfilm cracking. Typically, the a-Si films used can withstand between 1-2%strain before cracking.

In one aspect, the present invention relates to backplane and displaystructures designed to minimize the cracking problems in electro-opticdisplays. In other aspects, the present invention relates to variousimprovements in backplanes for electro-optic displays, components foruse in such backplanes and processes for the manufacture of suchbackplanes, which improvements may be useful in overcoming theaforementioned problems.

SUMMARY OF THE INVENTION

In one aspect, this invention provides an electro-optic displaycomprising:

-   -   a substrate;    -   a plurality of non-linear devices disposed substantially in one        plane on the substrate;    -   a plurality of pixel electrodes in electrical communication with        the non-linear devices;    -   a layer of electro-optic medium; and    -   a common electrode on the opposed side of the layer of        electro-optic medium from the pixel electrodes,    -   wherein the moduli of the various parts of the display are such        that, when the display is curved, the neutral axis or neutral        plane lies substantially in the plane of the non-linear devices.

This electro-optic display may hereinafter for convenience be called the“controlled moduli” display of the invention. In such a display, it isgenerally preferred that the neutral axis or neutral plane not deviatefrom the plane of the non-linear devices by more than about 5 percent,and desirably not more than about 1 percent, of the total thickness ofthe display. A layer of dielectric material may be interposed betweenthe non-linear devices and the pixel electrodes, and conductive viasprovided extending through the layer of dielectric material andconnecting the pixel electrodes to the non-linear devices.

In another aspect, this invention provides a process for producing aplurality of non-linear devices on a substrate, the process comprising:

-   -   forming an unpatterned layer of semiconductor material on the        substrate;    -   forming at least two discrete areas of metal overlying the        unpatterned semiconductor layer; and    -   etching the semiconductor layer using the discrete areas of        metal as a mask, thereby patterning the layer of semiconductor        material to leave at least two discrete areas of semiconductor        material underlying the at least two discrete areas of metal.

This process may hereinafter for convenience be called the “internalmask” process of the invention. This process may further comprisedepositing a dielectric layer over the layer of semiconductor materialbefore forming the at least two discrete areas of metal, and etchingboth the dielectric layer and the layer of semiconductor material in thesame etching step, thereby forming at least two discrete areas ofdielectric between the discrete areas of metal and the discrete areas ofsemiconductor material. Also, the at least two discrete areas of metalmay be formed by depositing an unpatterned layer of metal over thesemiconductor and thereafter patterning the layer of metal to form theat least two discrete areas of metal.

One useful form of the internal mask process comprises:

-   -   forming the unpatterned layer of semiconductor material on the        substrate;    -   forming at least two discrete areas of a first metal layer        overlying the layer of semiconductor material, each of the at        least two discrete areas forming an electrode of a transistor;    -   forming a dielectric layer overlying the first metal layer and        the layer of semiconductor material;    -   forming at least two discrete areas of a second metal layer        overlying the dielectric layer, each of the at least two        discrete areas forming an electrode of a transistor; and    -   etching the semiconductor layer using the first and second metal        layers as a mask, thereby patterning the layer of semiconductor        material to form at least two transistors on the substrate.

In another aspect, this invention provides a field effect transistorcomprising:

-   -   a semiconductor layer;    -   source and drain electrodes in electrical contact with the        semiconductor layer but spaced from one another so as to leave a        channel region of the semiconductor layer therebetween;    -   a gate dielectric layer superposed on the channel region of the        semiconductor layer; and    -   a gate electrode disposed on the opposed side of the gate        dielectric layer from the channel region, such that variation of        the voltage applied to the gate electrode can vary the        conductivity of the channel region of the semiconductor layer,        thus switching the transistor,    -   the gate dielectric layer extending over at least portions of        the source and drain electrodes adjacent the channel region, an        auxiliary dielectric layer being provided between the        overlapping portions of the gate dielectric layer and the source        and drain electrodes, the auxiliary dielectric layer not being        present in at least part of the channel region.

This transistor may hereinafter for convenience be called the “auxiliarydielectric” transistor of the invention. In such a transistor, theauxiliary dielectric layer may have a thickness at least twice as greatas that of the gate electrode, and may be formed from a low k dielectrichaving a dielectric constant not greater than about three times thedielectric constant of free space, for example silicon dioxide, apolyimide or a screen printable dielectric. The gate electrode may beformed by printing.

The auxiliary dielectric transistor of the invention is primarily,although not exclusively, intended for use as part of a transistor arraydesigned to drive an electro-optic display. In such a transistor arraycomprising at least two auxiliary dielectric transistors of theinvention disposed adjacent one another, the gate dielectric may becontinuous from one transistor to the other.

The present invention also provides a process (the “auxiliarydielectric” process of the invention) for forming an auxiliarydielectric transistor, this process comprising:

-   -   forming a layer of semiconductor material;    -   forming a layer of a conductive material superposed on the layer        of semiconductor material;    -   forming an auxiliary dielectric layer superposed on the layer of        conductive material;    -   patterning the auxiliary dielectric layer and the layer of        conductive material, thereby forming from the layer of        conductive material spaced source and drain electrodes separated        by a channel region of the layer of semiconductor material, such        that the auxiliary dielectric layer is removed from at least        part of the channel region;    -   forming a gate dielectric layer overlying at least the channel        region and adjacent portions of the source and drain electrodes;        and    -   forming a gate electrode superposed on the gate dielectric layer        and adjacent the channel region of the semiconductor layer.        In this auxiliary dielectric process, the gate electrode may be        formed by printing and the auxiliary dielectric layer may have a        thickness at least twice as great as that of the gate dielectric        layer.

In another aspect, this invention provides a process for producing atransistor, the process comprising:

-   -   forming a thin semiconductor layer;    -   printing spaced source and drain electrodes directly on to the        semiconductor layer leaving a channel region of the        semiconductor layer between the source and drain electrodes;    -   providing a gate dielectric layer superposed on the channel        region of the semiconductor layer; and    -   providing a gate electrode on the opposed side of the gate        dielectric layer from the channel region of the semiconductor        layer.

This process may hereinafter for convenience be called the “printed thinsemiconductor layer” process of the invention. In such a process, thethin semiconductor layer may have a thickness not greater than about 50nm, and may be formed of silicon.

In another aspect, this invention provides a backplane for anelectro-optic display, the backplane comprising a plurality of pixelelectrodes and a ring diode associated with each pixel electrode, eachdiode comprising at least one organic layer. This backplane mayhereinafter for convenience be called the “ring diode” backplane of theinvention. The backplane may further comprise at least one columnelectrode in electrical contact with a plurality of the ring diodes, thecolumn electrode being narrower than the layer of each ring diode inimmediate contact with the column electrode.

This invention extends to an electro-optic display comprising a ringdiode backplane of the present invention and a layer of electro-opticmedium disposed adjacent the backplane such that by varying the voltageson the pixel electrodes, the optical state of the electro-optic mediumcan be varied, the electro-optic medium having a threshold forswitching.

This invention also provides a backplane for an electro-optic display,the backplane comprising a plurality of pixel electrodes, a diodeassociated with each pixel electrode, and at least one column electrodein electrical contact with a plurality of the diodes, the columnelectrode being narrower than the layer of each diode in immediatecontact therewith. This backplane may hereinafter for convenience becalled the “narrow column electrode” backplane of the invention. In sucha backplane, the layer of each diode in immediate contact with thecolumn electrode may be organic. Alternatively, at least one diode maybe a metal-insulator-metal (MIM) diode.

This invention extends to an electro-optic display comprising a narrowcolumn electrode backplane of the present invention and a layer ofelectro-optic medium disposed adjacent the backplane such that byvarying the voltages on the pixel electrodes, the optical state of theelectro-optic medium can be varied, the electro-optic medium having athreshold for switching.

This invention also provides a backplane for an electro-optic display,the backplane comprising a column electrode, a dielectric orsemiconductor layer superposed on the column electrode, an upperdielectric layer superposed on the dielectric or semiconductor layer,and a pixel electrode superposed on the upper dielectric layer, thepixel electrode extending through an aperture in the upper dielectriclayer and contacting the dielectric or semiconductor layer, wherein thewidth of the area of contact between the pixel electrode and thedielectric or semiconductor layer is not greater than about one-fourthof the width of the column electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 of the accompanying drawings is a schematic section through acontrolled moduli display of the present invention.

FIGS. 2A to 2D are schematic top plan views illustrating various stagesof an internal mask process of the invention.

FIGS. 3 and 4 are schematic sections showing differing stages of anauxiliary dielectric process of the invention.

FIGS. 5A to 5D are schematic front elevations showing various stages ofa prior art process for forming a thin film transistor.

FIGS. 6A and 6B are schematic front elevations of an internal maskprocess of the invention.

FIG. 7 is a schematic front elevation of a printed thin semiconductorprocess of the invention.

FIG. 8 is a schematic section through one ring diode and adjacent partsof a ring diode backplane of the invention.

FIG. 9 is a schematic section, similar to that of FIG. 8, through amodified form of the ring diode backplane of FIG. 8, provided with anarrow column electrode.

FIG. 10 is a schematic section through an MIM diode usable in a narrowcolumn electrode backplane of the invention.

FIG. 11 is a schematic section through a second diode usable in a narrowcolumn electrode backplane of the invention.

DETAILED DESCRIPTION

As already indicated, this invention has several different aspectselectro-optic displays and to processes and components for theproduction of such displays. These various aspects will mainly bedescribed separately below, but it should be understood that a singledisplay, process or component may make use of more than one aspect ofthe invention. For example, FIG. 9 illustrates a single backplane whichmakes use of both the ring diode backplane and the narrow columnelectrode backplane aspects of the invention. To take another example, acontrolled moduli display of the invention may be manufactured by aninternal mask process of the invention.

Controlled Modulus Display

As already mentioned, this invention provides a controlled moduluselectro-optic display comprising a substrate; a plurality of non-lineardevices disposed substantially in one plane on the substrate; aplurality of pixel electrodes in electrical communication with thenon-linear devices; a layer of electro-optic medium; and a commonelectrode on the opposed side of the layer of electro-optic medium fromthe pixel electrodes. In this electro-optic display, the moduli of thevarious parts of the display are such that, when the display is curved,the neutral axis or neutral plane (i.e., the axis or plane in which nocompression or tension exists) lies substantially in the plane of thenon-linear devices. Desirably the neutral axis or neutral plane does notdeviate from the plane of the non-linear devices by more than about 5percent, and preferably not more than about 1 percent, of the totalthickness of the display.

One preferred form of the controlled modulus display uses a so-called“buried transistor” (or more accurately, “buried non-linear device”)design, in which a layer of dielectric material is interposed betweenthe non-linear devices and the pixel electrodes, and the pixelelectrodes are connected to the non-linear devices by conductive viasextending through the layer of dielectric material.

FIG. 1 of the accompanying drawings is a schematic section through acontrolled moduli display of the present invention. The displaycomprises a substrate 100, which is typically formed from a metal foil,stainless steel or a polyimide being especially preferred for thispurpose; a polyimide substrate will typically be about 50 μm inthickness. A thin film transistor layer 102 comprising a matrix of thinfilm transistors is formed on the substrate 100; in practice, asdescribed in the aforementioned 2002/0019081, if the substrate 100 isconductive, a thin dielectric layer is applied to insulate the thin filmtransistors from the substrate, but this dielectric layer is not shownin FIG. 1 (the individual transistors are also not shown in FIG. 1 forease of illustration). A layer of dielectric material 104 is disposedover the TFT layer 102; if the substrate 100 is formed of a dielectricmaterial such as a polyimide, the dielectric layer 104 is convenientlyformed of the same material. A plurality of pixel electrodes 106 areformed on the dielectric layer 104 and are connected to associatedtransistors (one transistor per pixel electrode) in the TFT layer 102 byconductive vias 108 extending through the dielectric layer 104. Finally,the display comprises a electro-optic layer 110 (illustrated as anencapsulated electrophoretic medium) and a front electrode 112, throughwhich an observer views the display. In practice, the front electrode112 is normally present as a layer of indium tin oxide or similartransparent conductive material on a front substrate, typically apolymeric film, which provides mechanical support to the front electrode112 and acts as a protective layer for the display, but this frontsubstrate is omitted from FIG. 1 for clarity.

The moduli of the various layers of the display are selected so that theneutral axis or neutral plane found when the display is curved lies atthe position indicated by 114, passing through the TFT layer 102.

The display shown in FIG. 1 may be prepared in the following manner:

-   -   (a) Begin with a 50 μm sheet of polyimide.    -   (b) Fabricate the thin film transistor layer consisting of a        gate metal, dielectric layer, a semiconductor layer, a contact        layer and a source/drain metal layer, in the manner described in        the aforementioned E Ink and MIT patents and applications;    -   (c) Deposit and cure or laminate a dielectric layer that is        mechanically similar to the substrate material, i.e., so that        the two materials substantially satisfy the relationship:

Y_(d)d_(d) ²=Y_(s)d_(s) ²

where Y_(d) and d_(d) are the elastic modulus and thickness of thedielectric layer, and Y_(s) and d_(s) are the elastic modulus andthickness of the substrate. When this equation is satisfied, thetransistors will lie in the neutral axis of the system resulting inminimal film strain. Depending on the compliance of subsequentelectro-optic medium and front plane material, one can recalculate theideal dielectric layer thickness;

-   -   (d) Pattern via holes in the dielectric layer to connect the        electrode material to the transistor circuits;    -   (e) Deposit via and pixel electrode material to complete the        circuit. Materials can be printed or ink jet or deposited using        vacuum techniques. These materials should be compliant in nature        and would ideally have the same mechanical properties of the        substrate and dielectric material;    -   (f) Deposit electro-optic medium and front plane electrode, for        example by lamination of a front plane laminate as described in        the aforementioned 2004/0027327.

The controlled moduli display aspect of the present invention allowsconstruction of an electro-optic display in which the transistor (orother non-linear element) layer is on the neutral axis and/or in theneutral plane, thus minimizing the tendency for cracking of the TFT orother non-linear element layers. The invention allows considerabledesign and material selection flexibility, and provides a highperformance flexible display backplane due to the symmetrical structuresurrounding the transistor or other non-linear element layer.

Internal Mask Process

As already mentioned, a second aspect of the present invention relatesto an “internal mask” process for producing a plurality of non-lineardevices on a substrate. This internal mask process comprises: forming anunpatterned layer of semiconductor material on the substrate; forming atleast two discrete areas of metal overlying the unpatternedsemiconductor layer; and etching the semiconductor layer using thediscrete areas of metal as a mask, thereby patterning the layer ofsemiconductor material to leave at least two discrete areas ofsemiconductor material underlying the at least two discrete areas ofmetal.

The internal mask process is designed to produce cost-effectivepatterning of a semiconductor layer to reduce leakage between adjacenttransistors in a transistor array. Obviously, all electrical circuitsrequire that adjacent independent elements be electrically isolated fromone another. For integrated circuits (i.e. circuits in which transistorsare formed on a common substrate or are constructed from a common film),electrical isolation prevents undesirable leakage currents betweenadjacent transistors. In the case of a thin film transistor array, suchas those used in active matrix backplanes, all transistors of the arrayare typically formed from a common semiconductor layer (film). Toprevent leakage between adjacent pixels, the semiconductor isconventionally patterned using photolithography, but this patterningstep represents a significant fraction of the total fabrication cost,and also introduces process complexity which makes high-volumemanufacturing more difficult. To avoid this cost and complexity, thesemiconductor may simply be left unpatterned, as described for examplein copending application Ser. No. 09/565,413, filed May 5, 2000 (nowU.S. Pat. No. 7,190,008). An unpatterned semiconductor necessarily tosome extent increases pixel leakage, making it more difficult tomaintain a charge stored on the pixel. This may have an adverse effecton the display performance, particularly for gray-scale applications.

The internal mask process of the present invention provides a processfor patterning a semiconductor without requiring an additionalphotolithography step. This is effected by using existing circuitfeatures, typically the electrodes of a transistor, as an etch mask forpatterning the semiconductor. These existing features (i.e. patternedlayers) are present in the transistor or other array independently ofwhether or not the semiconductor is patterned. A semiconductor presentbeneath such features may be patterned using the features as an etchmask.

FIGS. 2A-2D of the accompanying drawings illustrate, in a highlysimplified manner, one embodiment of such a process. In the first step(FIG. 2A) a uniform layer 200 of semiconductor is deposited on asubstrate. Next, as shown in FIG. 2B, a conductive layer formed, forexample of aluminum, a conductive polymer, or a conductive ink, iseither imagewise deposited, for example by printing, or coated andpatterned to form circuit features, illustrated as including columnelectrodes or data lines 202 (which also serve as the source electrodesof transistors, formed as described below), drain electrodes 204 andpixel electrodes 206 continuous with the drain electrodes 204; for easeof illustration FIGS. 2B-2D show the formation of only a two-by-twoarray of transistors although in practice of course a larger number oftransistors would be formed. A gate dielectric layer is then deposited,followed by another conductive film, which is either imagewisedeposited, for example by printing, or coated and patterned to form gateelectrodes 208 and their associated row electrodes (select lines) 210;see FIG. 2C. The source 202, drain 204 and gate 208 electrodes, thepixel electrodes 206 and the row and column electrodes 202 and 210 canthen be used as an etch mask to pattern the semiconductor withoutrequiring an additional photolithography step. For this purpose, thesemiconductor may be patterned using a plasma etch (for example, acarbon tetrafluoride etch) or a wet etch that etches the semiconductorwithout etching the circuit features used as a mask. The resultantpatterning of the semiconductor layer reduces undesirable leakagecurrents between neighboring pixels, without requiring any additionalphotolithography steps, as would be required in a conventional process,in which the semiconductor would be patterned using photolithographybetween the steps shown in FIGS. 2A and 2B.

Thus, the internal mask process of the present invention allows theproduction of a patterned semiconductor layer which requiring only thesame number of mask steps as the processes for forming unpatternedsemiconductor transistor arrays described in the aforementionedcopending application Ser. No. 09/565,413 and 2002/0106847. Thus, theinternal mask process enables good performance at reduced cost andcomplexity, as compared to a traditional process that usesphotolithography to pattern the semiconductor. Reducing the complexityof the process is an important factor in enabling high volumemanufacturing.

It will be appreciated that the internal mask process of the presentinvention may require redesign of certain circuits to be effective. Forexample, the transistors formed in FIGS. 2A-2D are top gate transistors,and the gate electrodes 208 prevent removal of areas of thesemiconductor layer 200 which form the channels of the transistors. Ifit is desired to use a bottom gate design, other circuit components mayneed to be repositioned to protect the channel regions of thesemiconductor layer 200.

Auxiliary Dielectric Layer Transistor and Process

As already mentioned, a third aspect of this invention provides anauxiliary dielectric field effect transistor comprising: forming theunpatterned layer of semiconductor material on the substrate; forming atleast two discrete areas of a first metal layer overlying the layer ofsemiconductor material, each of the at least two discrete areas formingan electrode of a transistor; forming a dielectric layer overlying thefirst metal layer and the layer of semiconductor material; forming atleast two discrete areas of a second metal layer overlying thedielectric layer, each of the at least two discrete areas forming anelectrode of a transistor; and etching the semiconductor layer using thefirst and second metal layers as a mask, thereby patterning the layer ofsemiconductor material to form at least two transistors on thesubstrate. The present invention also provides a process for formingsuch an auxiliary dielectric field effect transistor.

The auxiliary dielectric field effect transistor of the presentinvention is designed to reduce the gate to source-drain overlapcapacitance inherent in prior art transistor designs. The fabrication ofan active matrix backplane typically involves patterning and registeringfeatures with critical dimensions of less than 50 μm. Photolithographyis normally the only patterning technology that can meet thesedimensional requirements, but photolithography is a relatively expensiveprocess compared to other patterning technologies. Other morecost-effective patterning technologies, such as screen printing, areunable to meet the resolution/registration requirements of conventionalTFT structures, and backplanes and other devices fabricated using lowresolution patterning technologies usually suffer from degradedperformance (such as lower drive currents) due to the long channellengths and large parasitic source-drain/gate overlap capacitance of theresulting large transistors.

The auxiliary dielectric transistor of this invention enables highresolution patterning techniques to be replaced by low resolutionpatterning techniques without significantly degradation of deviceperformance. in the auxiliary dielectric transistor, the source/drainregions and the gate can be separated by a relatively thick auxiliary(and preferably low-k) dielectric, for example, silicon dioxide, BCB,polyimide, or a screen printable dielectric.

In conventional transistors, the source/drain electrodes and the gateelectrode are separated only by the gate dielectric. This imposescompeting requirements on the gate dielectric, so that the finaltransistor design is inevitably a compromise. To provide low parasiticgate to source/drain overlap capacitance, the gate dielectric should beas thick as possible and have a low dielectric constant. However, forgood device performance (as measured by parameters such as high drivecurrent, steep sub-threshold slope, etc.), the dielectric should be thinas possible and have a high dielectric constant.

The auxiliary dielectric transistor of this invention can decouple thesetwo competing requirements on the gate dielectric, and hence avoid theinevitable compromise present in conventional designs, by depositing thegate dielectric and the auxiliary dielectric, so that the auxiliarydielectric is not present in at least part of the channel regions of thetransistors. This use of two separate dielectrics results in reducedparasitic overlap capacitance or a larger maximum permissible overlap.If a large overlap is used, a low cost, low resolution patterning orprinting process may be used for the gate electrode, because thephysical dimension of the gate electrode can be much greater than thecritical dimension of the transistor, namely the channel length definedby the source to drain spacing. If the gate length is greater than thechannel length, there will be a large region in which the gate overlapsthe source and/or drain. This overlap is the source of a parasiticcapacitance which can adversely affect display performance by increasingRC gate line delay and the gate-to-pixel capacitance. This inventionminimizes these effects and thus allows the gate electrode to be formedusing a low-resolution patterning or printing process. The auxiliarydielectric transistor of this invention also reduces the layer-to-layerregistration requirements (by allowing more overlap). Low-resolutionpatterning processes are of course usually simpler and less costly thanhigh resolution processes such as photolithography.

A preferred auxiliary dielectric transistor and process of the inventionwill now be described, though by way of illustration only, withreference to FIGS. 3 and 4 of the accompanying drawings, which areschematic sections through an auxiliary dielectric transistor at twodifferent stages in its manufacturing process. As shown in FIG. 3, on asubstrate 300 is deposited an amorphous silicon (a-Si) layer 302, ametal layer 304 and a thick low-k (auxiliary) dielectric layer 306.Photolithography is used in the conventional matter to pattern both thedielectric layer 306 and the metal layer 304, but not the a-Si layer302, thus forming a source electrode S and a drain electrode D. Next, asshown in FIG. 4, a gate dielectric 308 is deposited over the entiresubstrate 300, and thereafter a gate electrode 310 is screen printed;since the overlap area between the gate 310 and the source and drainelectrodes is not critical, the gate 110 can be printed or otherwisedeposited using a low resolution process. It should be noted that thesemiconductor 302 may be deposited at several different points in theprocess (namely, either before the source/drain metal layer 304 isdeposited or after this metal layer has been patterned.

It should also be noted that the transistor structure shown in FIGS. 3and 4 does not require a heavily doped semiconductor for ohmic contactbetween the semiconductor and source/drain metal layer. The source/drainmetal layer may be directly in contact with the semiconductor. It shouldalso be noted that only the gate dielectric 308 and not the low kdielectric 306 is present over at least part of the area of the gateelectrode 310 so that in this area the gate can act on the semiconductorlayer 304 through only the relatively thin gate dielectric 308, and thegate electrode 310 is not required to act through the auxiliarydielectric 306.

The auxiliary dielectric process of the present invention reduces thecost and complexity of fabricating an active matrix backplane byallowing simple, low-cost patterning techniques to replace complex,expensive techniques such as photolithography. It also reduces thelayer-to-layer registration requirements. These features make theprocess more suitable for web-based manufacturing (compared to atraditional process using photolithography).

Printed Thin Semiconductor Process

As already mentioned, this invention provides a “printed thinsemiconductor” process comprising forming a thin semiconductor layer;printing spaced source and drain electrodes directly on to thesemiconductor layer leaving a channel region of the semiconductor layerbetween the source and drain electrodes; providing a gate dielectriclayer superposed on the channel region of the semiconductor layer; andproviding a gate electrode on the opposed side of the gate dielectriclayer from the channel region of the semiconductor layer. This processenables the production of thin film transistors with the source anddrain regions formed in a single printing step.

As indicated above, electro-optic displays require an inexpensivebackplane with adequate performance. Cost analysis shows thatphotolithography represents a significant fraction of the totalmanufacturing cost for silicon-based TFT's; vacuum processing (filmdeposition) is another source of manufacturing cost.

Also as already discussed, to reduce patterning cost, photolithographysteps may either be eliminated or replaced with a low-cost alternative.A silicon semiconductor active layer may be left unpatterned in exchangefor higher pixel-to-pixel leakage. The cost of metal patterning may bereduced by replacing photolithography with a lower-cost patterningtechnology. Various printing technologies (screen, offset, flexogravure)are possible replacements. However, in a conventional TFT, thesource/drain regions consist of highly doped silicon and a metal, bothof which are patterned. The highly doped semiconductor is required forohmic contact between the metal and semiconductor. Since doped siliconcannot be printed, “printing” the source-drain regions of such aconventional transistor in a single step is not currently possible.

The present invention relates to a process for producing transistor, inwhich process the use of a highly doped silicon layer is eliminated bythe use of a relatively thin semiconductor layer (cf. the aforementioned2002/0060321), and to a process for forming such a transistor byprinting.

FIGS. 5A-5D, 6A-6B and 7 illustrate the simplification of the processfor producing a transistor provided by the printed thin film process ofthe present invention. FIGS. 5A-5D illustrate the formation ofsource/drain regions of a transistor using a conventional processinvolving photolithography. In this process, there are deposited upon asubstrate 500 in order, a semiconductor layer 502, a highly dopedsemiconductor layer 504, a metal layer 506 and a layer of photoresist508. The photoresist layer 508 is then patterned to give the structureshown in FIG. 5A. In the next step, the metal layer 506 is etched usingthe photoresist 508 as a mask to give the structure shown in FIG. 5B. Asecond etch is then carried out using both the photoresist 508 and thepatterned metal layer 506 as a mask to etch the highly dopedsemiconductor layer 504 and produce the structure shown in FIG. 5C.Finally, the photoresist 508 is removed to give the final source/drainregion structure shown in FIG. 5D.

FIGS. 6A and 6B illustrate a simplified process in accordance with theinternal mask process of the present invention. In the process of FIGS.6A and 6B, there are deposited upon a substrate 600 in order, asemiconductor layer 602 and a highly doped semiconductor layer 604. Ametal or other conductive layer 606 is then printed over the highlydoped semiconductor layer 604 to give the structure shown in FIG. 6A.The highly doped semiconductor layer 604 is then etched using the metallayer 606 as a mask to give the final source/drain region structureshown in FIG. 6B.

FIG. 7 illustrates the simplified printed thin semiconductor process ofthe present invention. A thin layer 702 of semiconductor, typically lessthan 100 nm, and desirably less than 50 nm, of silicon, is depositedupon a substrate 700. A metal or other conductive layer 704 is thenprinted over the semiconductor layer 702 to give the final source/drainregion structure shown in FIG. 7. By using a thin semiconductor layer, ahighly doped silicon contact layer is not required; this results in asimple, low-cost process.

Thus, the printed thin semiconductor process of this invention allowsthe source/drain regions and electrode-forming metal layer to be formedin a single, low-cost step, as opposed to a conventional process, whichuses photolithography and requires multiple steps. The process reducesthe cost of silicon-based active matrix backplanes, and also reduces theprocess complexity (compared to a traditional process), thusfacilitating high-volume manufacturing.

Electro-Optic Displays with Diode Backplanes

As already mentioned, two aspects of the present invention relate toelectro-optic displays with diode backplanes, namely the ring diodebackplane and the narrow column electrode backplane.

It is known that backplanes for electro-optic displays can be made usingdiodes as the non-linear elements instead of the conventionaltransistors, and in principle a diode-based backplane should be lessexpensive than a transistor-based one. The cost savings should beespecially great if a type of diode could be employed based upon solubleorganic materials, since backplanes based upon such diodes could beproduced using solution processing and a process conducted completely atlow temperatures, in contrast to the processes used to producetransistor-based backplanes, which require vacuum processing and hightemperatures. However, there are two problems hindering the adoption ofdiode-based backplanes. Firstly, most of the types of electro-opticdisplays discussed above are polarity-sensitive, so that a backplanemust be capable of applying voltages of both polarities. Secondly,diodes have an inherent capacitance, and when the voltage applied to agiven pixel of the display changes, the inherent capacitance causes avoltage spike which may result in undesirable changes in the state ofthe electro-optic medium. The present invention provides diode-basedbackplanes designed to reduce or eliminate the aforementioned problems.

The ring diode aspect of the present invention provides a backplane foran electro-optic display, the backplane comprising a plurality ofpixels, each of which is provided with a ring diode. The ring diodeconducts in either direction in forward bias, and may be formed byforming a given diode structure and the same structure in reverse.

A preferred ring diode backplane of the present invention is illustratedin FIG. 8 of the accompanying drawings, which shows a schematic sideelevation of one pixel of an electro-optic display have a diode-basedbackplane. The electro-optic display comprises a backplane substrate 800on which a first metal layer is deposited and patterned to formelectrodes 802 and 802′. The display further comprises patterned firstand second organic layers 804 and 806 which together form an organicdiode; note that the layers 804 and 806 on the right-hand side of FIG. 8are reversed as compared with those on the left-hand side in order toprovide the desired ring diode structure. Finally, the display comprisesa pixel electrode 808, an electro-optic medium 810 (illustrated as anencapsulated electrophoretic medium) and a front electrode 812.

The narrow column electrode backplane aspect of the present inventionalso relates to a backplane for an electro-optic display. The narrowcolumn electrode backplane comprises a plurality of pixels, each ofwhich is provided with a diode. The column electrodes associated withthe diodes are of reduced width to reduce the capacitance of the diodes,and hence the voltage spikes which occur when the voltages applied tothe diodes are changed. Although the limited contact area of the reducedwidth column electrodes reduces the available drive current, this is notnormally a serious problem, since most solid electro-optic media requireonly small drive currents. The column electrodes are convenientlyreduced to the smallest width readily available using the technique usedto produce them, and typically not greater than about 25 μm.

FIG. 9 illustrates a modified version of the diode-based backplane ofFIG. 8 in which the widths of the electrodes 802 and 802′ have beengreatly reduced to provide narrow column electrodes 902 and 902′,resulting in a greatly reduced diode capacitance. The areas of thesubstrate covered by the organic layers 804 and 806 have been maintainedconstant, so that these organic layers in effect “wrap around” thenarrow column electrodes 902 and 902′. It will be appreciated that thesenarrow column electrodes 902 and 902′ could be replaced by a singlecolumn electrode centrally located between the two halves of the ringdiode and having only a small contact area with the organic layers 804and 806 thereof.

The use of narrow column electrodes is of course not confined to ringdiode-based backplanes of the type illustrated in FIG. 9. For example,FIG. 10 illustrates a metal-insulator-metal (MIM) diode having asubstrate 1000, a reduced width column electrode 1002, an insulatorlayer 1004 and a pixel electrode 1006.

FIG. 11 illustrates one pixel of a diode-based backplane with reducedcapacitance which is achieved in a different manner from that shown inFIGS. 9 and 10. The backplane shown in FIG. 11 comprises a substrate1100 bearing a column electrode 1102 of conventional width. Asemiconductor or insulator layer 1104 (the choice of layer 1104 ofcourse determined by whether an MIM diode or a metal-semiconductor-metaldiode is desired) having substantially the same width as the columnelectrode 1102 is superposed thereon. A thick dielectric layer 1106,which is desirably formed from a low k dielectric having a dielectricconstant not greater than about 3, is superposed on the layer 1104. Ametal pixel electrode 1108 is superposed on the dielectric layer 1106,except that a small area of the pixel electrode 1108 extends through anaperture formed in the dielectric layer 1106 and contacts the layer1104. Thus, the area of contact between the pixel electrode 1108 and thelayer 1104 is small relative to the size of the pixel electrode 1108,and the diode has a small inherent capacitance.

It will be appreciated that the pixel structure shown in FIG. 11 couldbe varied in several ways. For example, the size of the layer 1104 couldvary, since the only part of this layer which is effective in the diodestructure is that in contact with, or closely adjacent, the pixelelectrode 1108. Also, it should be understood that the thickness of thedielectric layer 1106 is greatly exaggerated in FIG. 11 relative to itswidth; for example, in practice the dielectric layer 1106 might be 5 μmthick, while the pixel electrode might be 200 μm square, so that any“dip” in the center of the pixel electrode where it is in contact thelayer 1104 would have minimal effect on the electro-optic performance ofthe pixel.

The width of the contact area between the pixel electrode and the layer1104 is desirably not greater than one-fourth and desirably not greaterthan one-tenth of the width of the column electrode 1102. Much smallerratios can be achieved; for example, a 200 μm wide pixel electrode, anda column electrode of the same width, with a 5 μm wide contact areabetween the pixel electrode and the layer 1104 would result in a 1:40ratio.

Even with a reduced width column electrode, there will be some residualinherent capacitance in each diode, and hence there will be some voltagespike during switching. Hence, the diode-based backplanes of the presentinvention are most suitable for use with electro-optic media having atleast a small threshold for switching. Such electro-optic medium with athreshold are known; see, for example copending application Ser. No.10/711,829 (Publication No. 2005/0168799).

It will be apparent to those skilled in the art that numerous changesand modifications can be made in the specific embodiments of the presentinvention described above without departing from the scope of theinvention. Accordingly, the whole of the foregoing description is to beconstrued in an illustrative and not in a limitative sense.

1. A field effect transistor comprising: a semiconductor layer; sourceand drain electrodes in electrical contact with the semiconductor layerbut spaced from one another so as to leave a channel region of thesemiconductor layer therebetween; a gate dielectric layer superposed onthe channel region of the semiconductor layer; and a gate electrodedisposed on the opposed side of the gate dielectric layer from thechannel region, such that variation of the voltage applied to the gateelectrode can vary the conductivity of the channel region of thesemiconductor layer, thus switching the transistor, the gate dielectriclayer extending over at least portions of the source and drainelectrodes adjacent the channel region, an auxiliary dielectric layerbeing provided between the overlapping portions of the gate dielectriclayer and the source and drain electrodes, the auxiliary dielectriclayer not being present in at least part of the channel region.
 2. Afield effect transistor according to claim 1 wherein the auxiliarydielectric layer has a thickness at least twice as great as that of thegate dielectric layer.
 3. A field effect transistor according to claim 1wherein the auxiliary dielectric layer is formed from a low k dielectrichaving a k value not greater than about
 3. 4. A field effect transistoraccording to claim 1 wherein the auxiliary dielectric layer is formedfrom silicon dioxide, a polyimide or a screen printable dielectric.
 5. Afield effect transistor according to claim 1 wherein the gate electrodeis formed by printing.
 6. A field effect transistor array comprising atleast two field effect transistors according to claim 1 disposedadjacent one another, wherein the gate dielectric is continuous from onetransistor to the other.
 7. A process for forming a field effecttransistor, the process comprising: forming a layer of semiconductormaterial; forming a layer of a conductive material superposed on thelayer of semiconductor material; forming an auxiliary dielectric layersuperposed on the layer of conductive material; patterning the auxiliarydielectric layer and the layer of conductive material, thereby formingfrom the layer of conductive material spaced source and drain electrodesseparated by a channel region of the layer of semiconductor material,such that the auxiliary dielectric layer is removed from at least partof the channel region; forming a gate dielectric layer overlying atleast the channel region and adjacent portions of the source and drainelectrodes; and forming a gate electrode superposed on the gatedielectric layer and adjacent the channel region of the semiconductorlayer.
 8. A process according to claim 7 wherein the gate electrode isformed by printing.
 9. A process according to claim 7 wherein theauxiliary dielectric layer has a thickness at least twice as great asthat of the gate dielectric layer.
 10. A process for producing atransistor, the process comprising: forming a thin semiconductor layer;printing spaced source and drain electrodes directly on to thesemiconductor layer leaving a channel region of the semiconductor layerbetween the source and drain electrodes; providing a gate dielectriclayer superposed on the channel region of the semiconductor layer; andproviding a gate electrode on the opposed side of the gate dielectriclayer from the channel region of the semiconductor layer.
 11. A processaccording to claim 10 wherein the semiconductor layer has a thicknessnot greater than about 50 nm.
 12. A process according to claim 10wherein the semiconductor layer is formed of silicon.
 13. A backplanefor an electro-optic display, the backplane comprising a plurality ofpixel electrodes, and a ring diode associated with each pixel electrode,each ring diode comprising at least one organic layer.
 14. A backplaneaccording to claim 13 further comprising at least one column electrodein electrical contact with a plurality of the ring diodes, the columnelectrode being narrower than the layer of each ring diode in immediatecontact with the column electrode.
 15. An electro-optic displaycomprising a backplane according to claim 13 and a layer ofelectro-optic medium disposed adjacent the backplane such that byvarying the voltages on the pixel electrodes, the optical state of theelectro-optic medium can be varied, the electro-optic medium having athreshold for switching.
 16. A backplane for an electro-optic display,the backplane comprising a plurality of pixel electrodes, a diodeassociated with each pixel electrode, and at least one column electrodein electrical contact with a plurality of the diodes, the columnelectrode being narrower than the layer of each diode in immediatecontact therewith.
 17. A backplane according to claim 16 wherein thelayer of each diode in immediate contact with the column electrode isorganic.
 18. A backplane according to claim 16 wherein at least onediode is a metal-insulator-metal diode.
 19. An electro-optic displaycomprising a backplane according to claim 16 and a layer ofelectro-optic medium disposed adjacent the backplane such that byvarying the voltages on the pixel electrodes, the optical state of theelectro-optic medium can be varied, the electro-optic medium having athreshold for switching.
 20. A backplane for an electro-optic display,the backplane comprising a column electrode, a dielectric orsemiconductor layer superposed on the column electrode, an upperdielectric layer superposed on the dielectric or semiconductor layer,and a pixel electrode superposed on the upper dielectric layer, thepixel electrode extending through an aperture in the upper dielectriclayer and contacting the dielectric or semiconductor layer, wherein thewidth of the area of contact between the pixel electrode and thedielectric or semiconductor layer is not greater than about one-fourthof the width of the column electrode.
 21. A process for producing aplurality of non-linear devices on a substrate, the process comprising:forming an unpatterned layer of semiconductor material on the substrate;forming at least two discrete areas of metal overlying the unpatternedsemiconductor layer; and etching the semiconductor layer using thediscrete areas of metal as a mask, thereby patterning the layer ofsemiconductor material to leave at least two discrete areas ofsemiconductor material underlying the at least two discrete areas ofmetal.
 22. A process according to claim 1 wherein the at least twodiscrete areas of metal are formed by depositing an unpatterned layer ofmetal over the semiconductor and thereafter patterning the layer ofmetal to form the at least two discrete areas of metal.